1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a semiconductor device of CMOS structure and to a manufacturing method therefor.
2. Description of Related Art
In association with recent improvement in the integration and miniaturization of semiconductor devices, the gate electrode of a MOSFET has become shorter, and a transistor having a gate length of 0.2 xcexcm or less is currently used. In a conventional CMOS structure, an n-channel MOSFET is formed along the surface of a wafer, whereas a p-channel MOSFET is formed so as to be embedded in the wafer. As the gate length becomes shorter, it becomes difficult to reduce a threshold voltage (Vth) of an embedded p-channel transistor which shows noticeable short channel characteristics. For this reason, there has been employed a p-channel MOSFET which is also formed along the surface of the wafer. As a result, there has been employed a dual gate structure in which the gates of n-channel and p-channel MOSFETs are used as gates.
FIGS. 24 through 29 show a method of manufacturing a conventional semiconductor device employing a dual gate structure. With reference to FIGS. 24 through 29, a flow of manufacture of a conventional semiconductor device will now be described in sequence.
As shown in FIG. 24, trench isolation structures 2 are formed in the surface of a p-type silicon substrate 1, thus dividing the surface of the substrate 1 into the trench isolation structures 2 and remaining active regions 3 and 4. Through photolithography and implantation, the active regions are transformed respectively into a p-well 3 and an n-well 4.
As shown in FIG. 25, a gate oxide film 5 is formed over the trench isolation structures 2, the p-well 3, and the n-well 4. Subsequently, a non-doped polycrystalline silicon layer 15 is formed on the gate oxide film 5.
As shown in FIG. 26, through photolithography a resist mask 16 is formed on the non-doped polycrystalline silicon layer 15. The non-doped polycrystalline silicon layer 15 that remains on the p-well 3 is doped with Phosphor (P) ions 18 implanted at 30 KeV and 2E15 cmxe2x88x922, whereby the thus-doped area of the polycrystalline silicon layer 15 is transformed into an n-type polycrystalline silicon layer 6.
As shown in FIG. 27, through photolithography a resist mask 16 is formed on the non-doped polycrystalline silicon layer 15 that remains over the p-well 3. The non-doped polycrystalline silicon layer 15 that remains on the n-well 4 is doped with boron (B) ions 19 implanted at 20 KeV and 2E15 cmxe2x88x922, whereby the thus-doped area of the polycrystalline silicon layer 15 is transformed into a p-type polycrystalline silicon layer 7. The wafer is again subjected to photolithography in order to pattern gate electrodes, and gate electrodes are formed through etching by use of a resist mask.
FIG. 28 shows the wafer after the gate electrodes have been formed by etching. In FIG. 28, the gate electrode of the n-channel MOSFET is formed from the n-type polycrystalline silicon layer 6 (a gate electrode 6) and the oxide film 5 (a gate oxide film). The gate electrode of the p-channel MOSFET is formed from a p-type polycrystalline silicon layer 7 (a gate electrode 7) and the oxide film 5 (a gate oxide film). As shown in FIG. 28, a lightly doped drain (LDD) region (Nxe2x88x92) 8 of the n-channel MOSFET and a lightly doped drain (LDD) region (Pxe2x88x92) 9 of the p-channel MOSFET are each formed through photolithography and ion implantation.
As shown in FIG. 29, through CVD side walls 10 are formed from an oxide film on both sides of each of the gate electrodes 6 and 7. An N+ source/drain region 11 of the n-channel MOSFET and a P+ source/drain region 12 of the p-channel MOSFET are each formed through photolithography and ion implantation.
According to the method of manufacturing a conventional dual gate semiconductor device having the previously-described surface channel type P-MOSFET, at the time of formation of gate electrodes a non-doped polycrystalline silicon is deposited on the surface of a wafer, and the wafer surface is formed into n-type and p-type regions through ion implantation by use of a mask. Thus, addition of the photolithography and ion implantation steps renders the manufacturing processes complicate. A polycrystalline silicon layer formed through ion implantation contains an insufficient amount of doped impurities in contrast with a polycrystalline silicon layer which is doped with phosphor ions during deposition. As a result, a gate region is depleted of carriers. Further, since there is a difference in etch rate between etching of n-type polycrystalline silicon and p-type polycrystalline silicon at the time of formation of a gate electrode through etching, unetched portions of the polycrystalline silicon may remain on the wafer or etching may not be blocked by the gate oxide film, thereby etching away the substrate beneath the gate oxide film. Thus, a difference in etch rate renders manufacture of a semiconductor device difficult. Furthermore, there may arise a boron (B) penetration phenomenon, in which boron (B) ions implanted for the purpose of forming a p-type polycrystalline silicon layer penetrate through the gate oxide film in a subsequent heat treatment process, thus deteriorating the reliability of the gate oxide film.
For these reasons, a desirable gate structure is not a dual gate structure comprising n-type and p-type MOSFETs which are formed on a single polycrystalline silicon substrate, but a single gate structure doped with either n-type or p-type impurities. When a semiconductor device is manufactured through use of a single gate structure, a MOSFET which is of either an n-channel or a p-channel must be formed so as to become embedded in the substrate, in order to prevent the threshold voltage (Vth) from becoming excessively high. Further, the short channel characteristics may become noticeable in the embedded channel MOSFET.
FIGS. 30 through 35 show a surface channel MOSFET of single gate structure, and account for an increase in the threshold voltage Vth by reference to a p-channel MOSFET. FIG. 30 shows an energy band in a depthwise direction in a dual gate structure in which a p-type polycrystalline silicon layer is formed on the n-well, particularly showing a flat-band state of the dual gate structure. In FIG. 30, the vertical axis depicts energy applied to holes, and Ev represents a valence band; Ec represents a conduction band; Ef represents a Fermi level; Ei represents an intrinsic potential; and Vg represents a gate potential. In the flat band state shown in FIG. 30, there is a difference between the Fermi level Ef and the gate potential Vg. The reason for this is that, in the n-well, the Fermi level Ef is in the vicinity of the conduction band, and, since the gate is of p-type, the gate potential Vg is in the vicinity of the valence band.
FIG. 31 shows an energy band in a case where Vg=0V. As shown in FIG. 30, there is a difference between the Fermi level Fe and the gate potential Vg in the flat band state. For this reason, the energy band is bent so as to eliminate the difference, as shown in FIG. 31. Therefore, even when Vg=0V, the energy band is bent in a direction in which the transistor is turned on; specifically, in a direction in which an inverted channel can be established.
FIG. 32 is an energy band in a case where Vg=Vth. As shown in FIG. 31, the energy band is bent toward a direction in which the transistor is turned on, even when Vg=0V, and the threshold voltage Vth required to turn on the transistor assumes a value of about 0.6V. An explanation is now given of a single gate structure in which an n-type polycrystalline silicon layer is formed on the n-well.
FIG. 33 shows a flat band state of the single gate structure. As shown in FIG. 33, since the gate electrode is also of an n-type, the gate potential Vg becomes close to the conduction band Ec in close proximity to the Fermi level Ef. Accordingly, when Vg=0V as shown in FIG. 34, the energy band is substantially identical with the flat band and is not bent.
FIG. 35 shows an energy band when Vg=Vth. As shown in FIG. 34, the gate potential Vg originally assumes a value of 0V and is close to the flat band. As shown in FIG. 35, the gate voltage Vg required to induce inverted carriers becomes nearly 0.8V higher than the gate voltage Vg required for the dual gate structure; namely, the threshold voltage assumes a value of about 1.4V. Thus, when a surface-type p-channel MOSFET is formed through use of n-type polycrystalline silicon, the threshold voltage becomes higher.
As mentioned above, in a case where a semiconductor device is manufactured by use of a dual gate structure, the threshold voltage Vth becomes too high unless MOSFETs of either a p-channel or n-channel are formed so as to be embedded in the substrate. If the MOSFETs are formed so as to become embedded in the substrate, the short channel characteristic becomes noticeable. In contrast, in a case where a surface-type p-channel MOSFET is formed into a single gate structure by use of n-type polycrystalline silicon, the threshold voltage Vth becomes high.
Accordingly, the present invention has been conceived to solve the aforementioned problems, and the object of the present invention is to provide a semiconductor device comprising surface-type n-channel and p-channel single gate transistors by formation of fixed charges within a gate oxide film, and to provide a manufacturing method therefor.
According to a first aspect of the present invention, there is provided a semiconductor device comprising: a semiconductor substrate of first conductivity type; a well of first conductivity type formed on the surface of the semiconductor substrate of first conductivity type; a well of second conductivity type formed on the surface of the semiconductor substrate of first conductivity type; a gate dielectric film formed over the well of first conductivity type and the well of second conductivity type through thermal oxidation; a polycrystalline silicon layer of second conductivity type formed on the gate dielectric film; a gate formed by etching the polycrystalline silicon layer of second conductivity type; a side wall formed from an oxide film on the gate through CVD oxide film; and fixed electric charges of second conductivity type within the gate dielectric film.
According to a second aspect of the present invention, there is provided a method of manufacturing a semiconductor device comprising the steps of: forming a trench isolation region in the surface of a semiconductor substrate of first conductivity type; forming the trench isolation region and active regions including a well of first conductivity type and a well of second conductivity type; forming a gate dielectric film over the trench isolation region and the active regions through thermal oxidation; forming a polycrystalline silicon layer of second conductivity type on the gate dielectric film; forming a gate by etching the polycrystalline silicon layer of second conductivity type; forming a side wall formed on the gate through CVD oxide film; and forming fixed electric charges of second conductivity type within the gate dielectric film by application of a voltage across the gate and the well of second conductivity type, and by implantation of electric charges of second conductivity type at high energy from the semiconductor substrate.
The above and other objects, effects, features and advantages of the present invention will become more apparent from the following description of the embodiments thereof taken in conjunction with the accompanying drawings.